The present invention relates to a quadrature phase correction circuit, and more particularly, to a quadrature phase correction circuit that can reduce a layout size by decreasing the number of code counters.
Synchronous semiconductor devices input and output data in synchronization with a clock signal. Such synchronous semiconductor devices include clock signal generators for generating an internal clock signal synchronized with an external clock signal. One of the clock signal generators is a quadrature phase signal generator to generate a quadrature phase clock signal having a 90-degree phase difference from an external clock.
FIG. 1 is a block diagram of a conventional quadrature phase correction circuit.
Referring to FIG. 1, the conventional quadrature phase correction circuit includes a quadrature phase correction (QPC) controller 10, a phase detection circuit 12, a duty cycle correction circuit 14, and a phase error correction circuit 16. The phase detection circuit 12 detects phases of in-phase (I) and quadrature (Q) clock signals fed back. The duty cycle correction circuit 14 performs a duty cycle correction on an external I-clock signal and an external Q-clock signal according to the phase difference detected by the phase detection circuit 12. The phase error correction circuit 16 corrects the phase error of an I-clock signal ICLK_DC and the Q-clock signal QCLK_DC whose duty cycles are corrected by the duty cycle correction circuit 14.
The phase detection circuit 12 includes an N-bit code counter 24, an initial code control (ICC) circuit 22, and a phase detector (I-DCD(I-IB)) 20. The N-bit code counter 24 sets and stores code values for correction according to the I-clock signal and offset values of components in an initial operation. The ICC circuit 22 performs an initial code control according to the code values set in the code counter 24. The phase detector 20 receives the I-clock signal ICLK_DC and the IB-clock signal IBCLK_DC fed back after the offset value is adjusted by the ICC circuit 22, and generates a high signal or a low signal according to the phase detection. The IB-clock signal IBCLK_DC represents an inversion signal of the I-clock signal ICLK_DC.
The phase detector 20 compares a phase of the I-clock signal with a phase of the IB-clock signal when a strobe signal (not shown) applied from a quadrature phase correction (QPC) controller 10 is at a high level or a low level. The phase detector 20 generates the high signal when the phase of the I-clock signal ICLK_DC is greater than that of the IB-clock signal IBCLK_DC, and generates the low signal when the phase of the I-clock signal ICLK_DC is less than that of the IB-clock signal IBCLK_DC.
In addition, the phase detection circuit 12 includes an N-bit code counter 30, an ICC circuit 28, and a phase detector (Q-DCD(Q-QB)) 26. The N-bit code counter 30 sets and stores code values for correction according to the Q-clock signal and offset values of components in an initial operation. The ICC circuit 28 performs an initial code control according to the code values set in the code counter 30. The phase detector 26 receives the Q-clock signal QCLK_DC and the QB-clock signal QBCLK_DC fed back after the offset value is adjusted by the ICC circuit 28, and generates a high signal or a low signal according to the phase detection. The QB-clock signal QBCLK_DC represents an inversion signal of the Q-clock signal QCLK_DC.
The phase detector 26 compares a phase of the Q-clock signal with a phase of the QB-clock signal when a strobe signal (not shown) applied from the QPC controller 10 is at a high level or a low level. The phase detector 26 generates the high signal when the phase of the Q-clock signal QCLK_DC is greater than that of the QB-clock signal QBCLK_DC, and generates the low signal when the phase of the Q-clock signal QCLK_DC is less than that of the QB-clock signal QBCLK_DC.
Furthermore, the phase detection circuit 12 includes an N-bit code counter 36, an ICC circuit 34, and a phase detector (QPD(I-Q)) 32. The N-bit code counter 36 sets and stores code values for correction according to the I-clock signal and the Q-clock signal, whose duty cycles are corrected, and offset values of components. The ICC circuit 34 performs an initial code control according to the code values set in the code counter 36. The phase detector 32 receives the I-clock signal ICLK_PC and the Q-clock signal QCLK_PC fed back after the offset value is adjusted by the ICC circuit 34, and generates a high signal or a low signal according to the phase detection.
The phase detector 32 compares a phase of the I-clock signal ICLK_PC with a phase of the Q-clock signal QCLK_PC when a strobe signal (not shown) applied from the QPC controller 10 is at a high level or a low level. The phase detector 32 generates the high signal when the phase of the I-clock signal ICLK_PC is greater than that of the Q-clock signal QCLK_PC, and generates the low signal when the phase of the I-clock signal ICLK_PC is less than that of the Q-clock signal QCLK_PC.
The duty cycle correction circuit 14 includes an N-bit code counter 40 and an I-IB duty cycle correction circuit 42. The N-bit code counter 40 sets code values by increasing or decreasing the code values according to the high/low value detected by the phase detector 20. The I-IB duty cycle correction circuit 42 corrects the duty cycles of the I-clock signal ICLK_E and the IB-clock signal IBCLK_E according to the code values set by the N-bit code counter 40. The I-clock signal ICLK_DC and the IB-clock signal IBCLK_DC, whose duty cycles are corrected by the I-IB duty cycle correction circuit 42, are fed back to the phase detector 20. The I-clock signal ICLK_E and the IB-clock signal IBCLK_E input to the I-IB duty cycle correction circuit 42 are clock signals that are generated using an external reference clock signal by a clock generator (not shown).
In addition, the duty cycle correction circuit 14 includes an N-bit code counter 44 and a Q-QB duty cycle correction circuit 46. The N-bit code counter 44 sets code values by increasing or decreasing the code values according to the high/low value detected by the phase detector 26. The Q-QB duty cycle correction circuit 46 corrects the duty cycles of the Q-clock signal QCLK_E and the QB-clock signal QBCLK_E according to the code values set by the N-bit code counter 44. The Q-clock signal QCLK_DC and the QB-clock signal QBCLK_DC, whose duty cycles are corrected by the Q-QB duty cycle correction circuit 46, are fed back to the phase detector 26. The Q-clock signal QCLK_E and the QB-clock signal QBCLK_E input to the Q-QB duty cycle correction circuit 46 are clock signals that are generated using an external reference clock signal by a clock generator (not shown).
The phase error correction circuit 16 includes an N-bit code counter 48 and a I-Q phase error correction circuit 50. The N-bit code counter 48 sets code values by increasing or decreasing the code values according to the high/low value detected by the phase detector 32. The I-Q phase error correction circuit 50 corrects the phases of the I-clock signal ICLK_DC and the Q-clock signal QCLK_DC according to the code values set by the N-bit code counter 48. The I-clock signal ICLK_PC and the Q-clock signal QCLK_PC, whose phases are corrected by the I-Q phase error correction circuit 50, are fed back to the phase detector 32. The I-clock signal ICLK_DC and the Q-clock signal QCLK_DC input to the I-Q phase error correction circuit 50 are clock signals, whose duty cycles are corrected by the duty cycle correction circuits 42 and 46, respectively. The QPC controller 10 generates enable signals for controlling the operations of the phase detectors 20, 26 and 32, the duty cycle correction circuits 42 and 46, and the phase error correction circuit 50, and the strobe signals to the phase detectors 20, 26 and 32.
The operation of the conventional quadrature phase correction circuit will be described below.
FIG. 2 is a timing diagram illustrating the operations of the respective units included in the conventional quadrature phase correction circuit.
The I-clock signal and the offset values of the components are adjusted by the ICC circuit 22 in the initial operation. To this end, the phase detector 20 receives the I-clock signal and the regulated I-clock signal (first reference signal) and detects the phase difference of the two signals. In this case, the phase detector 20 compares the I-clock signal with the regulated I-clock signal (first reference signal) when the strobe signal output from the QPC controller 10 is at a high level or a low level. The phase detector 20 outputs the high signal when the I-clock signal is greater than the regulated I-clock signal (first reference signal), and outputs the low signal when the I-clock signal is less than the regulated I-clock signal (first reference signal). The first reference signal is a reference value that is separately input for initial code setting.
The N-bit code counter 24 resets the code value by increasing the previously stored code value by 1 when the phase detector 20 outputs the high value, and by decreasing the previously stored code value by 1 when the phase detector 20 outputs the low value. The ICC circuit 22 controls the offset value of the phase detector 20 according to the code value reset to the N-bit code counter 24. Generally, the ICC circuit for controlling the offset value of the phase detector 20 includes a plurality of units that differently control the offset value of the phase detector 20 according to the code values, and the offset value corresponding to the reset code value is set to the phase detector.
Likewise, the Q-clock signal and the offset values of the components are adjusted by the ICC circuit 28 in the initial operation. To this end, the phase detector 26 receives the Q-clock signal and the regulated Q-clock signal (second reference signal) and detects the phase difference of the two signals. In this case, the phase detector 26 compares the Q-clock signal with the regulated Q-clock signal (second reference signal) when the strobe signal output from the QPC controller 10 is at a high or low level. The phase detector 26 outputs the high signal when the Q-clock signal is greater than the regulated Q-clock signal (second reference signal), and outputs the low signal when the Q-clock signal is less than the regulated Q-clock signal (second reference signal). The second reference signal is a reference value that is separately input for initial code setting.
The N-bit code counter 30 resets the code value by increasing the previously stored code value by 1 when the phase detector 26 outputs the high value, and by decreasing the previously stored code value by 1 when the phase detector 26 outputs the low value. The ICC circuit 28 controls the offset value of the phase detector 26 according to the code value reset to the N-bit code counter 30. Generally, the ICC circuit for controlling the offset value of the phase detector 26 includes a plurality of units that differently control the offset value of the phase detector 26 according to the code values, and the offset value corresponding to the reset code value is set to the phase detector.
Furthermore, the I-clock signal (or the Q-clock signal) and the offset values of the components are adjusted by the ICC circuit 32 in the initial operation. To this end, the phase detector 32 receives the I-clock signal (or the Q-clock signal) and a third reference signal and detects the phase difference of the two signals. In this case, the phase detector 32 compares the I-clock signal with the third reference signal when the strobe signal output from the QPC controller 10 is at a high or low level. The phase detector 32 outputs the high signal when the I-clock signal is greater than the third reference signal, and outputs the low signal when the I-clock signal is less than the third reference signal. The third reference signal is a reference value that is separately input for initial code setting.
The N-bit code counter 36 resets the code value by increasing the previously stored code value by 1 when the phase detector 32 outputs the high value, and by decreasing the previously stored code value by 1 when the phase detector 32 outputs the low value. The ICC circuit 34 controls the offset value of the phase detector 32 according to the code value reset to the N-bit code counter 36. Generally, the ICC circuit for controlling the offset value of the phase detector 32 includes a plurality of units that differently control the offset value of the phase detector 32 according to the code values, and the offset value corresponding to the reset code value is set to the phase detector.
Through the above-described processes, the offset of the phase detector 20 is adjusted by the control value of the ICC circuit 22, and the offset of the phase detector 26 is adjusted by the control value of the ICC circuit 28. Also, the offset of the phase detector 32 is adjusted by the control value of the ICC circuit 34. At this point, the initial code control values are set and stored in the corresponding N-bit code counters 24, 30 and 36.
After adjusting the initial code value, the phase detection operations of the phase detectors 20, 26 and 32 and the operations of the duty cycle correction circuits 42 and 46 and the phase error correction circuit 50 are controlled by the control signals provided from the QPC controller 10.
That is, the QPC controller 10 generates the enable signals ICC_IDCDEN, ICC_QDCDEN and ICC_QPDDEN for controlling the operations of the phase detectors 20, 26 and 32. Although not illustrated, the QPC controller 10 generates the strobe signals which will be output to the respective phase detectors.
The phase detector 20 is operated in response to the enable signal ICC_IDCDEN output from the QPC controller 10, and compares the I-clock signal and the IB-clock signal when the strobe signal is at the high level or the low level. The I-clock signal ICLK_DC and the IB-clock signal IBCLK_DC are feedback signals output from the I-IB duty cycle correction circuit 42, which will be described later. The phase detector 20 outputs the high signal when the I-clock signal ICLK_DC is greater than the IB-clock signal IBCLK_DC, and outputs the low signal when the I-clock signal ICLK_DC is less than the IB-clock signal IBCLK_DC.
The N-bit code counter 40 resets the code value by increasing the previously stored code value by 1 when the phase detector 20 outputs the high signal, and by decreasing the previously stored value by 1 when the phase detector 10 outputs the low signal.
The I-IB duty cycle correction circuit 42 is operated in response to the enable signal IDCCEN output from the QPC controller 10 and corrects the duty cycles of the I-clock signal ICLK_E and the IB-clock signal IBCLK_E according to the code value reset to the N-bit code counter 40. Generally, the duty cycle correction of the duty cycle correction circuit 42 is achieved by providing a plurality of units that differently control the duty cycle of the output signal of the duty cycle correction circuit 42 according to the code values, and setting the duty cycle value corresponding to the reset code value to the duty cycle correction circuit 42.
Likewise, the phase detector 26 is operated in response to the enable signal ICC_QDCDEN output from the QPC controller 10, and compares the Q-clock signal QCLK_DC and the QB-clock signal QBCLK_DC when the strobe signal is at the high level or the low level. The Q-clock signal QCLK_DC and the QB-clock signal QBCLK_DC are feedback signals output from the Q-QB duty cycle correction circuit 46, which will be described later. The phase detector 26 outputs the high signal when the Q-clock signal QCLK_DC is greater than the QB-clock signal QBCLK_DC, and outputs the low signal when the Q-clock signal QCLK_DC is less than the QB-clock signal QBCLK_DC.
The N-bit code counter 44 resets the code value by increasing the previously stored code value by 1 when the phase detector 26 outputs the high signal, and by decreasing the previously stored value by 1 when the phase detector 26 outputs the low signal.
The Q-QB duty cycle correction circuit 46 is operated in response to the enable signal QDCCEN output from the QPC controller 10 and corrects the duty cycles of the Q-clock signal QCLK_E and the QB-clock signal QBCLK_E according to the code value reset to the N-bit code counter 44. Generally, the duty cycle correction of the duty cycle correction circuit 46 is achieved by providing a plurality of units that differently control the duty cycle of the output signal of the duty cycle correction circuit 46 according to the code values, and setting the duty cycle value corresponding to the reset code value to the duty cycle correction circuit 46.
The phase detector 32 is operated in response to the enable signal ICC_QPDDEN output from the QPC controller 10, and compares the I-clock signal ICLK_PC and the Q-clock signal QCLK_PC when the strobe signal is at the high level or the low level. The I-clock signal ICLK_PC and the Q-clock signal QCLK_PC are feedback signals output from the I-IB/Q-QB duty cycle correction circuits 42 and 46, respectively. The phase detector 32 outputs the high signal when the I-clock signal ICLK_PC is greater than the Q-clock signal QCLK_PC, and outputs the low signal when the I-clock signal ICLK_PC is less than the Q-clock signal QCLK_PC.
The N-bit code counter 48 resets the code value by increasing the previously stored code value by 1 when the phase detector 32 outputs the high signal, and by decreasing the previously stored value by 1 when the phase detector 32 outputs the low signal.
The I-Q phase error correction circuit 50 is operated in response to the enable signal QPCEN output from the QPC controller 10 and corrects the phases of the I-clock signal ICLK_DC and the Q-clock signal QCLK_DC according to the code value reset to the N-bit code counter 48. Generally, the phase correction of the I-Q phase error correction circuit 50 is achieved by providing a plurality of units that differently control the phase correction of the I-clock signal and the Q-clock signal output from the phase error correction circuit 50 according to the code values, and setting the phase correction value corresponding to the reset code value to the phase error correction circuit 50.
Through the above-described processes, the duty cycle correction value of the I-IB duty cycle correction circuit 42 is set based on the code value set by the N-bit code counter 40, and the duty cycle correction value of the Q-QB duty cycle correction circuit 46 is set based on the code value set by the N-bit code counter 44. The phase correction value of the I-Q phase error correction circuit 50 is set based on the code value set by the N-bit code counter 48.
The conventional quadrature phase correction circuit includes the N-bit code counters 24, 30 and 36 in order to set the initial code values of the phase detectors 20, 26 and 32. Specifically, the initial code values of the phase detectors 20, 26 and 32 are set based on the values set and stored in the N-bit code counters 24, 30 and 36. In addition, the phase differences detected by the phase detectors 20, 26 and 32 are set and stored in the N-bit code counters 40, 44 and 48. Furthermore, the code values for the duty cycle correction values of the duty cycle correction circuits 42 and 46 and the phase correction value of the phase error correction circuit 50 are set.
Therefore, the conventional quadrature phase correction circuit needs a total of six code counters in order to correct the phases of the I-clock signal and the Q-clock signal. However, since the six code counters occupy a large area, there is a difficulty in the fabrication of the semiconductor devices.